Static Random Access Memory (SRAM) has the advantages of high speed, lower power consumption and compatibility with standard semiconductor fabrication processes. SRAMs are widely used in computers, communication devices, and consumer electronics products (e.g., smart card, digital camera, multimedia player, etc.).
As the feature sizes of the integrated circuit technology continue to shrink, multi-gate devices become more popular. For example, FinFET is widely used in SRAM transistors and enhances the performance of SRAM transistors.
FIG. 1 illustrates a schematic top view of an SRAM memory cell formed by using FinFET. FIG. 1 only shows the fin part and the gate electrode of each transistor.
The SRAM memory cell includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4.
The first PMOS transistor P1 and the second PMOS transistor P2 are pull-up transistors. The first NMOS transistor N1 and the second NMOS transistor N2 are pull-down transistors. The third NMOS transistor N3 and the fourth NMOS transistor N4 are transfer transistors.
In a high performance SRAM memory cell with high performance, the pull-down transistors need a higher drive current than the pull-up transistors to satisfy the memory performance requirement. The ratio of the drive current among the pull-down transistors N1, N2, the pull-up transistors P1, P2, and the transfer transistors N3, N4 is approximately 2:1:1. Because the area of the transistor channel region is proportional to transistor drive current, the ratio of the area of the transistor channel region among the pull-down transistors N1, N2, the pull-up transistors P1, P2, and the transfer transistors N3, N4 is approximately 2:1:1.
In a conventional fabrication process, the fin part of a FinFET has the same height as the gate structure formed in the same SRAM memory cell. Transistors formed with a single fin part have the same channel region area. The pull-down transistors N1, N2 have two fin parts. The pull-up transistors P1, P2 and the transfer transistors N3, N4 only need one fin part. The pull-down transistors N1, N2 have twice as much channel region area as the pull-up transistors P1, P2 and the transfer transistors N3, N4. This type of SRAM structure increases the number of fin parts required to form a static memory cell, and hence fails to increase the integration density of static memory devices.